THE M FLAG one bit doubles the accumulator — the same opcode, 8 or 16 bits wide
In native mode the M status bit sets the width of the accumulator: M=1 and it is 8 bits (the 6502), M=0 and it is 16. The instruction bytes do not change — A9 is still “load A immediate” — but it now consumes one operand byte or two, and arithmetic wraps at 0xFF or 0xFFFF depending on M. It is width as a runtime flag rather than a new instruction set: the same program, the same opcodes, twice the register. The permutation carried in a single status bit.
THE TECHNIQUE M=1 → 8-bit A, M=0 → 16-bit A — same opcodes
The demo masks the same value 0x1234 by the M flag — 8-bit gives 0x34, 16-bit gives 0x1234: live demo
HISTORY & CREDIT 65C816 status bit M
“A 16-bit CPU needs 16-bit opcodes.” — the 65816 reuses the 6502’s and lets one status bit choose the width. cited
the bit · M in the status byte — accumulator width, chosen at runtime. the reuse · the same opcode byte, now 8- or 16-bit; operands and wrap follow M. the pair · M for the accumulator, X for the index registers (dart 457) — independent widths.
A register that grows or shrinks on one bit — width made a flag, not a fork in the instruction set. width flag
RECOMMEND FOR I-13 the width switch, on the compiler
On the canonical compiler, the same 0x1234 is 0x34 (52) under M=1 and 0x1234 (4660) under M=0:
$ i13 run pm_mflag.i13 # accumulator mask by M
RUN OK · 36 step(s) · peak stack 3 · call depth 1
a8 = 52 -- M=1: 8-bit
a16 = 4660 -- M=0: 16-bit
width_switch = 1
Recommend as a NULL — configuration, not an axis. The M flag parameterizes the width of a fixed operation; choosing 8 vs 16 bits is a representation/encoding choice (B44), and every correct 65816 masks the same way (B39). No carried channel, no new invariant — the same computation at two resolutions. NULL — the elegant heart of how the permutation reuses the whole 6502 opcode map.