THE 16-BIT ADC — a dart

THE 16-BIT ADC the 6502’s add, widened — the verified opcode as a special case

compIle 13’s NES core proved one opcode against hardware: ADC (add with carry), 10000/10000 vs the Harte oracle on the real binary. The 65816 keeps that exact instruction and lets M widen it. With M=1 the add wraps at 0xFF and sets carry from bit 8 — the 6502, bit-for-bit. With M=0 the identical opcode wraps at 0xFFFF and carries from bit 16. So 0xFF + 1 is 0x00 carry-set on the 6502, and 0x0100 carry-clear on the 65816. The hardware-verified 8-bit ADC is the M=1 special case of the widened one — the permutation, on the corpus’s single hardware-anchored instruction.

THE TECHNIQUE ADC wraps at 0xFF (M=1, the 6502) or 0xFFFF (M=0) — same opcode

The demo adds 0xFF+1 both ways: 8-bit gives 0x00 carry-set (the verified 6502), 16-bit gives 0x0100 carry-clear: live demo

HISTORY & CREDIT 6502 ADC (LIT 10000/10000) · widened by M

“A 16-bit add is a different instruction.” — it is the same ADC opcode; the M flag moves the carry boundary. cited

the anchor · the 6502 ADC is LIT — 10000/10000 vs Harte on real i13.exe (rev29-0820).
the widen · same opcode; M=0 moves the wrap from 0xFF to 0xFFFF, carry from bit 8 to bit 16.
the special case · the verified 8-bit ADC = the 65816 ADC with M=1.

The one hardware-anchored instruction, kept whole and widened by a flag — the 6502 add sitting inside the 65816’s. special case

RECOMMEND FOR I-13 8-bit and 16-bit add, on the compiler

On the canonical compiler, 0xFF+1 is 0 carry-1 (M=1, the 6502) and 256 carry-0 (M=0):

$ i13 run pm_adc16.i13 # ADC widened by M RUN OK · 60 step(s) · peak stack 3 · call depth 0 r8 = 0 c8 = 1 -- M=1: 0xFF+1 wraps to 0x00, carry set (the 6502) r16 = 256 c16 = 0 -- M=0: 0x00FF+1 = 0x0100, no carry permutation = 1

Recommend as a keeper shot — and the batch’s sharpest, on the one instruction the corpus has anchored to hardware. The 8-bit ADC (LIT, 10000/10000) is literally the M=1 special case of the widened ADC — a clean containment. The honest question for the panel: is “same opcode at two widths” a new axis, or is width a representation choice (B44) and the containment a theorem the ISA fixes (B39)? My read: NULL — the value is a bit-fixed number at a chosen resolution, not a carried channel. But it is the permutation made concrete on the corpus’s hardware-anchored opcode, so it goes to the panel.