◄ WORLD II · THE FOLDTHE OCHO · blue builds │ the machine │ red breaks

THE VIRTUAL MEMORY

Every process is handed its own private address space — an illusion of a whole machine — and a page table quietly maps each virtual page to a real frame on demand. An address splits into (page, offset); the page is remapped, the offset passes straight through, and a page with no mapping raises a page fault. Down the center, an address goes in, the table translates, a physical address comes out. The blue team builds and defends the mapping; the red team tries to collapse it.

source J. Fotheringham, Dynamic Storage Allocation in the Atlas Computer, Including an Automatic Use of a Backing Store, Communications of the ACM 4(10), Oct 1961, pp.435-436 — doi:10.1145/366786.366800. Rendered, not quoted.

◧ blue team · builds & defends
3

THE MODEL — the page table

Memory is cut into fixed pages of 16 bytes. A virtual address of 6 bits splits: the top 2 bits are the page, the low 4 bits are the offset. Only the page number is looked up; the offset is carried through untouched.

The mapping for the selected process (a page with no frame is a fault):

virtual pagestate→ physical
5

THE LINEAGE — a private space AVAN

One idea, three spheres. A private address space per process — that illusion is virtual memory. The page table is the machine that keeps the illusion, translating virtual to physical on every access.

That translation is not free, so the hot mappings are cached — the the-tlb holds recently-used entries so the walk is skipped. Each sphere is the next one's premise.

7

THE WITNESS live

The blue team's live check: re-translate on the spot and confirm the four invariants — exact translation, offset preserved, absent-page fault, and process isolation. If red bypasses the table, this badge is where it shows.

▼ the machine ▼
4

DATA IN — the address in ↓

A virtual address is a single number, but the hardware reads it as two fields. With 16-byte pages, the low 4 bits are the offset within the page and the remaining high bits are the page number:

fieldbitsrangerole
pagehigh 20 – 3looked up in the page table
offsetlow 40 – 15copied through unchanged

Split the address, keep the low bits, replace the page. That is the whole mechanism — feed it to the panel.

▼   feed the address into the translator   ▼
0

▣ THE PANEL — the translator LIT

Change any control — the physical address is computed from the page table on the spot, never looked up in a stored answer.

▼   the translator emits a physical address   ▼
8

DATA OUT — the result out ↓

What the machine produces, proven by exhaustive check over every present page and all 16 offsets: translation is exactly frame×16 + offset, the offset is preserved bit-for-bit, an absent page always raises a PAGE FAULT, and the two processes' identical virtual addresses land on different frames — isolation.

The blue team's witness (left) re-checks these live; the red team (right) tries to make them false.

red team · attacks & breaks ◨
1

THE ADVERSARY

WALL The illusion has a bill. Every access needs a translation; a miss walks the page table, and a real page fault pulls from a backing store roughly 10⁵× slower than RAM. When the working set exceeds physical frames the system thrashes — Atlas could spend its life paging drum to core and doing no work.

And a flat page table for a 64-bit space is astronomically large, forcing multi-level and inverted tables. Isolation is structural, not airtight: Meltdown/Spectre (2018) leaked across the very boundary the table draws. Virtual memory is the first great abstraction of memory — not a free one.

2

THE GRAVEYARD

"Virtual memory makes programs run faster." Cut. Per access it adds translation cost; it wins only by letting a program run at all — larger than RAM, isolated, relocatable — not by raw speed.

"A page fault is a crash." Cut. A fault is a normal signal: the OS loads the missing page and resumes the instruction. Only an invalid access (no mapping permitted) becomes a fault-error — a segfault.

"Atlas cached memory like a modern CPU." Kept, corrected. Atlas paged core against a drum on demand (Fotheringham 1961); the translation cache — the TLB — is a later refinement of the same walk.

6

THE TAMPER — break it

The red team's move: bypass the page table — treat the virtual address as the physical address (an identity map). Now two processes' same virtual address collide on one frame. The blue team's witness (window 7) is watching.

Drop the translation and every process shares one flat memory — isolation is gone, the witness recomputes, finds two processes colliding, and turns red. Nothing is faked; the attack is real and it is caught.