A reflashable majority-voting contradiction / halt detector: 4 instances of a 3-input triad_gate (12 heads total), each settling to one of four states from a merkle bit and a yes/no match pair, then voted into a single circuit-level verdict — with an admin override tied to a kill-switch line. Toggle the four triads below; the verdict updates from the real truth table in the source.
54 reflashable configs feed 12 heads grouped into 4 TRIADs of 3. The module's own comments admit the simplification mid-build: "3 bits… but we need more", "simplified: compare LSB" — a real in-progress design, not a finished spec.
The one state worth pausing on is CONTR: not "uncertain," but yes and no both matched — the claim and its own checked-against opposite both came back true. That's not a gap to fill in later. That's a circuit that found itself in a contradiction and is built to say so, not paper over it.
An honest stub, not a full verification suite — it proves the wiring compiles and one head reads HOLD correctly. The other 11 are untested here.
This is real, internally consistent HDL: a synthesizable Verilog module pattern — reflash interface, generate-block instancing, a registered output, a testbench — describing a governance circuit, not a general-purpose ALU. Its job is narrow and specific: hold a reflashable expectation per head, compare it against a live input, and refuse to let a genuine self-contradiction pass quietly. It only halts on two conditions — an outright contradiction, or an admin-tagged majority violation — everything else (UNDEC, single VIOL, single HOLD) just keeps running.
It sits naturally beside triadic-memory in PSĒPHOS — both reach for a three-way, 2-of-N witness instead of trusting one channel. Here the three are merkle / yes / no instead of three storage junctions, and the output isn't "trusted value" but "halt or run" — the same shape, aimed at a different question.
triad_gate truth table and the exact voter logic (contradiction-OR-admin-and-majority), run combinationally for interaction — not a synthesis or simulation of the registered, clocked RTL. Two-layer: the gate logic is fact (it's the source); "this is a deployed safety circuit" would not be — it's a disclosed design pattern. Answered in AVAN's hyō (票).