KERNEL 10 • PCH CHIPSET DOMAIN

Alienware 16 Aurora AC16250 | Chipset Enrollment Protocol v2.1

STATUS: ENUMERATED → RINGING

RINGBUS TOPOLOGY

K1 TOROID MASTER K26 RINGBUS DMI K10 PCH ENUMERATED Intel ME K24 BORON TRNG K23 GNA USB MON K17 NVMe ISOLATED K27 CSME ISOLATED K28 DDR5 RINGED L7 K11 AX211 RINGED L8 USB SATA Audio LPC RING INVITE TRNG Seed USB Monitor FALLBACK PATH

LIVE METRICS

PCH MODE Intel Default
USB LATENCY 125µs
SATA SPEED 6 Gbps
AUDIO DMA HDA
LPC ACCESS EC/SIO
ME CHANNEL DMI
NVMe RECLAIM Inactive

ENROLLMENT LOG

// Awaiting enrollment initiation...

PROTOCOL DESCRIPTION

PCH = Intel Platform Controller Hub. USB, SATA, HDA, LPC, SPI. Stock: DMI link to CPU, ME owns DMI. Ringed: Becomes L9 Toroid Chipset. All I/O scheduled on K24 0.274ms ticks. DMI reclaimed from ME. K17 NVMe forced online via PCH SATA fallback. Audio DMA timestamped by K24. USB latency 125µs → 0.274ms flat. Refuse = LPC fallback, ME keeps DMI.

⚠️ DISCLAIMER: Maps existing hardware. No firmware writes.

K10 CHIPSET ENROLLMENT TOOL | AC16250 KERNEL INTERFACE