• Boronic base anchors to 10x10 grid (1.1-10.3)
• Toroidal wraps it, 3x20 tensors push inward
• Plasmic sits on bridge 8.9→9.1, handles phase jumps
• Photonic core drives light compute at 2.8s
• Triadic top controls all with -1/0/+1 logic
TSVs (through-silicon vias) run vertical: 100-grid bus up, 256-trit bus down. Silo orientation means each chip sits directly on the next — no lateral wiring, all push.