Wired 10x10x10 Kernel Board

README.md - Wired 10x10x10 Kernel Board Layout

Overview

This simulation models a 3D neuromorphic photonic array with 100 Ag₂S quantum dot cores arranged in a 10x10 grid. Each core is wired via Ti₃SiC₂ MAX phase traces with ZnO dielectric fill between layers. Photons propagate at 2 m/s through Ti waveguides, get trapped in Ag₂S dots for 15µs, then release to modulate output current.

Board Architecture

• Layer 0 - Substrate: Si wafer base with Cu ground plane
• Layer 1 - Ti₃SiC₂ Traces: 10x10 grid of photonic waveguides, 50nm thick
• Layer 2 - ZnO Fill: Dielectric isolation, 100nm between traces
• Layer 3 - Ag₂S Cores: 100 quantum dots at grid intersections, 20nm diameter
• Layer 4 - Au Contacts: Edge contact pads for IN/OUT/O1 signals

Material Properties

• S - Sulfur: Photon carrier, 850nm wavelength pulses
• Ti - Titanium: Ti₃SiC₂ MAX phase, low-loss photonic waveguide
• Cu - Copper: Electrical interconnects, 35µm traces
• Zn - Zinc: ZnO piezoelectric fill, modulates with pressure
• Ag - Silver: Ag₂S quantum dot, 15µs carrier lifetime
• Au - Gold: Contact pads, wirebond interface

Operation

• Build 10x10x10: Instantiate 100 cores in grid layout with Ti trace routing
• IN Pulse: Inject photon into Ti waveguide at grid edge
• 10kHz Clock: Synchronize photon release from Ag₂S traps
• O1 Button: Enable/disable O1 output channel gating
• Pressure Slider: Apply 0-100 kPa to ZnO layer, modulates D value 0.0-1.0
• D Value: Per-core synaptic weight, pressure + photon history dependent
• OUT Current: Summed output: Σ(D_i × I_photon_i)

Physics Model

Photons travel at v = 2 m/s in Ti₃SiC₂. On Ag₂S collision, 85% trapping probability for t_trap = 15µs. Pressure modulates ZnO permittivity affecting coupling efficiency. Current output follows I_OUT = Σ D_i × 0.1µA when O1 enabled.