How does a circuit REMEMBER? Cross two gates so each feeds the other, and the pair gets stuck in whichever state it was last pushed into — it holds. Poke Set and it’s a 1 forever; poke Reset and it’s a 0; let go and it keeps the last answer. One bit of memory from feedback alone. Slide through a sequence and watch it remember.
Two cross-coupled NOR gates: Q = NOR(R, Q̄) and Q̄ = NOR(S, Q). Set (S=1,R=0) forces Q=1; Reset (S=0,R=1) forces Q=0; and Hold (S=0,R=0) leaves Q at its last value — that is the memory, made of nothing but feedback. S=R=1 is forbidden (it drives both outputs to 0, breaking Q=¬Q̄). A fail-loud self-check settles the loop and throws unless set→1, reset→0, BOTH hold states retain their prior bit, and the S=R=1 state is caught as forbidden — the SR latch, the atom of every register.
An asynchronous SR latch — real designs gate it with a clock (making a D flip-flop) and mind setup/hold timing and metastability. The truth table, the memory in the hold state, and the forbidden input are exact.