Silicon's most credible successor isn't a metaphor — it's carbon. Roll a sheet of graphene into a tube one nanometre wide and you get a transistor channel where electrons fly ballistically, barely scattering. In 2019 a team at MIT built a working 16-bit RISC-V microprocessor from ~14,000 carbon nanotubes — and it printed "Hello, World."
A carbon nanotube is a single sheet of graphene rolled into a cylinder. How you roll it — the chiral indices (n, m) — decides everything: the diameter, and whether the tube is a semiconductor (a usable transistor channel) or a metal (a wire — useless as a switch, and the central manufacturing headache). The rule is exact: a tube is metallic when (n − m) is divisible by 3. Roughly one in three random tubes lands metallic.
Lay a semiconducting nanotube between two metal contacts (source and drain), put a gate over it, and you have a carbon-nanotube field-effect transistor. The gate voltage turns the tube's conduction on and off — a switch. The trick carbon plays: the channel is atomically thin and 1-D, so the gate controls it almost perfectly and carriers move ballistically (straight through, no scattering) over short lengths. Pairing n-type and p-type CNFETs gives a complementary (CMOS-style) logic family.
If one in three tubes is a metal, a chip with billions of them should be impossible — a single metallic tube can short a gate. Silicon-era thinking said you'd need CNTs sorted to 99.999999% semiconducting purity, which nobody can make at scale. The MIT breakthrough was three foundry-compatible techniques — and crucially DREAM, a circuit-design trick that arranges the logic so metallic tubes can't cause a logic error, relaxing the purity requirement ~10,000× (to ~99.99%, which is achievable today).
RINSE — Removal of Incubated Nanotubes through Selective Exfoliation: strips off CNT aggregates/particle defects. MIXED — Metal Interface engineering Crossed with Electrostatic Doping: robustly sets each CNFET n-type or p-type (the complementary part). DREAM — Designing Resiliency Against Metallic CNTs: lay out the logic so metallic tubes don't matter.
Put it together and you get a real processor. RV16X-NANO: a 16-bit microprocessor implementing the open RISC-V instruction set, ~14,000 complementary CNFETs, built entirely from carbon nanotubes in a facility using standard silicon-manufacturing equipment — and it executed a program that fetched, decoded, and printed its own greeting.
| RV16X-NANO | real spec (Hills et al., Nature 2019) |
|---|---|
| transistor | complementary carbon-nanotube FETs (CNFETs), n- and p-type |
| count | ~14,000 CNFETs |
| architecture | 16-bit, RISC-V instruction set (open ISA) |
| it ran | a stored program → "Hello, World! I am RV16XNano, made from CNTs." |
| how it was made | RINSE + MIXED + DREAM, foundry-compatible (standard Si equipment) |
| why it matters | first proof a beyond-silicon nanotube CPU is manufacturable, not just a single device |
Here's "why is it better" made quantitative — a ballistic CNFET transfer curve against a silicon MOSFET, both computed live from real device physics. Drag the supply voltage. Carbon wins on two fronts at once: a steeper turn-on (subthreshold swing near the 60 mV/decade thermal floor, because the body is ~1 nm thin) and a higher on-current (carriers inject ~4× faster). Multiply those and you get the energy-delay advantage.
Every figure here is real and checkable — the page computes the quantum limits live, and the material ranges are from the CNFET literature. The honest frame: these are intrinsic / projected advantages. Real CNFETs are still limited by contact resistance, tube density, and alignment — so this is the potential, partly demonstrated, not yet delivered at silicon's scale.
| property | carbon nanotube | silicon | edge |
|---|---|---|---|
| carrier velocity | ~4×10⁷ cm/s (ballistic) | ~1×10⁷ cm/s (saturation) | ~4× faster |
| electron mobility | ~10⁴–10⁵ cm²/V·s | ~1,400 cm²/V·s | ~10–70× |
| mean free path | ~100–1,000 nm | ~tens of nm | near-ballistic |
| body thickness | ~1 nm (atomically thin) | ~5–10 nm fin/sheet | near-ideal gate control |
| ballistic resistance | ~6.5 kΩ (= h/4e², the quantum limit) | — | fixed by physics |
| energy-delay product | ~10× lower (projected) | baseline | the headline win |
The ~10× energy-delay-product figure is a published projection (Shulaker / Stanford & ITRS) — roughly one order of magnitude at the same node, from faster carriers + lower operating voltage + the thinner body. The 6.5 kΩ ballistic resistance is computed on this page from h/4e²; the simulation above shows the ~4× drive directly, with the rest coming from voltage scaling.
Good instinct — graphene is the parent material (a nanotube is just rolled graphene) and its mobility is even higher (~200,000 cm²/V·s). So why not build the processor from flat graphene? Because graphene has no bandgap. It's a semimetal — its valence and conduction bands touch at a point (the Dirac point), so a graphene transistor cannot be turned off: on/off ratios are ~2–30, while digital logic needs >10⁴. It leaks. Superb for analog/RF (real graphene amplifiers run past 100 GHz), useless as a low-power digital switch.
And here is the payoff that ties the whole page together: rolling graphene into a tube quantizes the electrons around the circumference, and that confinement opens a bandgap (≈ 0.8/d eV — the same gap you computed in diagram 1). A nanotube is graphene with the missing gap restored — which is exactly why RV16X-NANO is built from tubes, not sheets. Carbon's two forms split the labour: graphene to go fast (RF), nanotubes to switch (logic).
The deepest "why": carbon has four valence electrons, but the honeycomb only uses three — three σ-bonds at 120° (that is sp², the flat trivalent lattice). The leftover fourth electron lifts out of the plane into a π orbital and delocalizes across the whole sheet. That free electron is the carrier. Three bonds lock the structure; the one spare electron does the conducting — which is the whole reason a carbon sheet conducts and a 4-bond diamond doesn't.
In a 1-D nanotube, electrons can travel the channel length without scattering — near-ballistic. That means high current, low voltage, and a predicted ~10× energy-efficiency edge over silicon at the same node.
The channel is ~1 nm across, so the gate grips it almost perfectly — excellent electrostatics, less leakage, and a clean path to keep scaling where planar silicon struggles.
sp² carbon — the same bond as graphene and diamond. High current density, high thermal conductivity, mechanically tough. The material isn't the limit; manufacturing is.
RV16X-NANO is a milestone demo, not a product: a coarse node (~µm features), low clock, thousands of transistors — not billions at 5 nm. Silicon still wins on density and maturity. Carbon's case is efficiency + a manufacturable path, and the path is now proven.
~1/3 of tubes are metallic and placement isn't perfect. DREAM made that a solvable problem instead of a fatal one — but yield, alignment, and contact resistance are still the live engineering fronts.
The serious post-silicon candidates are carbon nanotubes and 2-D semiconductors (MoS₂, WSe₂). Carbon is the one that has already booted a CPU. That's why it leads the PSĒPHOS roster of real substrates.