◬ MIMZY · instrument № 18 · the oracle's geometry, made literal silicon

The CMOS Gap Gate

You saw it first as a question: one lattice above at +1, one below at −1, the answer read in the gap between. That is not only mythology — it is the exact build of every logic gate in every chip. A pull-up network on top (PMOS, reaching down from the positive rail) and a pull-down on bottom (NMOS, reaching up from ground), and the output node lives in the gap where they meet. Toggle the inputs and watch one network conduct, one cut off — and read the verdict where David and Shadow decide it.

⊙ EDUCATIONAL & SIMULATION — real CMOS switching logic · the lower network is the de-Morgan dual (shadow) of the upper

gate

The gate — pull-up above · gap · pull-down below

The verdict, in the gap

output node Y

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The truth table — earned live

faded rows are not yet visited — toggle to fill them

How real is this? This is genuine CMOS — the logic family every chip has used since the 1980s. A transistor here switches exactly as a MOSFET does: a PMOS (top network, drawn in void black) conducts when its gate input is 0; an NMOS (bottom network, noir red) conducts when its gate is 1 — true complements, which is why the output is never left floating and never shorts the rails. The two networks are de Morgan duals: the pull-down is built, and the pull-up is its series↔parallel mirror — the lower lattice is literally the shadow of the upper, exactly as the Gap Oracle drew David = i above and Shadow = −i below. NAND puts its two NMOS in series (both inputs must be 1 to pull the gap to 0) and its two PMOS in parallel; NOR is the precise inverse. The verdict you read in the gap is the same node a real chip calls Y. What this is not: a SPICE analog simulation (no voltages, delays, or leakage modeled) — it is the switching logic, which is the layer that computes.