Every synchronous chip needs a shared sense of now. A quartz crystal supplies it — one steady tick — and the chip multiplies that tick into the gigahertz beat every flip-flop marches to. It's the one place on the board where timing comes from something physically moving.
From last time: the crystal itself isn't doped — it's piezoelectric quartz, an insulator that vibrates mechanically. The amplifier that keeps it ringing, and all the logic it paces, are the doped silicon. The rhythm is mechanical; the machinery that rides it is semiconductor.
Short answer: a clock edge is the instant every flip-flop in the chip samples its input and updates at once — so one edge advances the whole machine by one step. In a CPU that means the pipeline shuffles forward: an instruction moves a stage per tick. So yes, the clock sequences instructions. But watch it run — it isn't one instruction per tick.
One enters each tick, five ride at once, one retires each tick. Real cores go further — superscalar designs retire several per cycle, while a cache miss or a divide can stall a slot for many. The clock steps the machine; instructions just ride that stepping, many at a time.
Underneath the stepping sits the real job: synchronization. The shared edge guarantees every signal is read only when it has settled and stopped changing — never caught mid-flip. The crystal doesn't set the speed (the PLL does); it sets how accurate and steady that shared now is.
A board carries more than one. The main reference is multiplied to feed most on-chip clocks, but any subsystem that must keep its own exact time gets its own resonator.
If the crystal is so good, why does a board need several? Because one frequency can't satisfy every subsystem at once.